Insulated gate devices, such as MOSFETs in particular, are used in many applications as synchronous rectifiers. In this case, the insulated gate device operates as a diode: it is turned on when the equivalent diode must be in conduction and is turned off when the diode must stop conducting.
This happens for example in output bridge stages in DC-DC converter applications.
In these applications, the intrinsic bipolar diode (body-drain junction) is switched, but such an intrinsic diode is inefficient because:                it switches slowly;        it has a high conduction voltage;        it may generate EMI in the boardand this limits the efficiency of the whole system.        
In order to reduce the switching time or more precisely the reverse recovery time of the diode (trr), techniques for controlling the life time of minority carriers are generally used. The introduction in the semiconductor substrate of the device of Au, Pt, or other elements by ion implantation, or irradiation with electrons, produces a marked decrease of the life time (from tens of microseconds to tens of nanoseconds) with consequent reduction of the trr of the intrinsic or internal diode. In any case, the reduction of the trr is accompanied by an increase of the conduction voltage (Vf) and of the output resistance (Ron) of the insulated gate device that limits the usefulness of such techniques.
Moreover, these techniques amplify or do not reduce the problems due to a too fast recovery of the diode and thus to the emissions of electromagnetic interferences (EMI) on the board. In order to improve softness, more complex alternative techniques are needed.
A known approach is that of using a Schottky diode of the same voltage and of appropriate area, in parallel to the internal PN junction diode of the integrated structure of the insulated gate device (for example a power MOS transistor or briefly PMOS).
Because of the absence of minority carriers, the Schottky diode is characterized by a fast recovery and, because of the different barrier heights, it has lower conduction voltages. In fact, for voltages lower than 0.9V the Schottky diode conducts a larger current than a PN junction diode; for higher voltages, the characteristics become similar and the PN diode finally conducts a larger current, because of the modulation of its conductivity.
Therefore, the parallel of a junction diode and a Schottky diode produces an equivalent device with the following characteristics:                reduced Vf at relatively low current levels (<0.8V);        less stored charge and thus reduction of the switching time.        
FIG. 1 illustrates the advantage of a combined diode MPS (Merged PN Schottky) in respect to a normal junction diode.
The experimental trade-off curve between Vf and the inverse current peak during the switching of a MPS diode upon varying the area of the Schottky diode and when the control of the life time in a PN diode has been obtained by irradiating the junction with high energy electrons (3 MeV) at doses comprised between 0 and 32 MRad.
Nowadays, various Schottky diode configurations, in parallel with the intrinsic diode of the PMOS structure are implemented in planar devices to be used in the low voltage range (320-150 V): that is from the simplest architecture that uses a single package but separate devices (discrete solution) depicted in FIG. 2, to more complex architectures that integrate the Schottky diode in the PMOS structure itself.
Among known “integrated” solutions, there is the one shown in FIG. 3, according to which a separated area (on the same chip) is dedicated for the Schottky diode. However, this solution has limitations and drawbacks, as will be explained later.
A more efficient solution, depicted in FIG. 4, consists in “distributing” the Schottky diode uniformly over the whole active area of the PMOS by integrating it in the elementary cells of the MOS. It has been demonstrated that by using a uniform distribution of Schottky diodes, it is possible to improve the dynamic performances (trr and softness) while using a reduced total area dedicated to the diode.
A solution of this kind, for low voltages devices, is disclosed in the U.S. Pat. No. 5,886,383.
According to the technique described in the patent, a Schottky diode is realized in the elementary cell of the MOSFET by a dedicated step of photolithography for realizing a Schottky diode through a certain aperture produced through a first deposited polysilicon layer, that is in the area destined to the realization of the integrated structure of an elementary cell of the insulated gate power device and on which the relative source contact will be established.
Commonly, Schottky diodes are realized by contacting with a metal layer the monocrystalline semiconducting substrate, the doping level of which determines the voltage class. In order to improve electric characteristics (leakage and breakdown voltage) when not conducting, it is well known the technique of forming, around the Schottky contact region in the semiconductor, a more or less dense array of juxtaposed diffuse regions (tubs) of opposite type of conductivity to that of the substrate (Lateral Merged PiN Schottky). The distance of separation among adjacent tubs is chosen so that under conditions of inverse polarization, the electric field is partially shielded by the depleted zones that form around the tubs.
Summarizing, in order to co-integrate Schottky diodes within the cellular structure of a power MOS there are two different approaches:    1) Schottky diode formed in dedicated areas inside the power MOS. In this case, areas more or less distributed are defined within the active area of the MOS structure, on which a Schottky contact is realized through the process steps that are done for realizing the integrated MOS structure. As explained before, in order to limit leakage current, the Schottky diode contact is surrounded by diffusions of opposite type of conductivity to that of the semiconductor crystal for shielding the electric field that is created under inverse polarization. The shielding diffusions may be realized by the same body implant of the MOS or by a dedicated implant step.    2) Schottky diode integrated in the single elementary cells that constitute the power MOS. Even if more efficient, this approach is little used because it imposes layout restraints severely limiting the possibility of increasing the packing density. The known techniques, such as the technique described in the above mentioned U.S. Pat. No. 5,886,383, require the realization of an island (51 of FIG. 4) of oxide or photoresist within an aperture produced through the polysilicon layer (poly). This limits the possibility of reducing the width of the aperture and represents an obstacle to increase the packing density of the elementary cells of the integrated structure of the power device. The shielding diffusions of the Schottky diode must necessarily be realized with the same implant step of the body of the MOS.